In recent years, with increasing demand for higher packing density of semiconductor devices, the miniaturization of internal elements, such as a transistor, and the multi-layering of wiring have been advancing. Particularly, the performance of wiring comes to exert a large influence on the performance of a semiconductor device, and thus the damascene process is introducing copper wiring of low resistance in place of aluminum wiring.
FIGS. 8A and 8B are a plan view for showing a chip area in a conventional wafer and a partial plan view for showing, through an insulating film, the neighborhood of a chip area corner portion of a semiconductor device provided in the chip area. Also, FIG. 9 is a cross sectional view of the conventional semiconductor device, taken along a VIII—VIII line shown in FIG. 8B.
As shown in FIGS. 8A and 8B and FIG. 9, this semiconductor device comprises a silicon substrate 101, element isolation 102 formed on the silicon substrate 101 and enclosing an active region 103, a diffusion layer 104 formed in the active region 103, a first interlayer insulating film 110 provided on the silicon substrate 101, a second interlayer insulating film 114 provided on the first interlayer insulating film 110, a third interlayer insulating film 118 provided on the second interlayer insulating film 114, a fourth interlayer insulating film 121 provided on the third interlayer insulating film 118, and a humidity-resistant insulating film 124 provided on the fourth interlayer insulating film 121. Further, in the chip area outer periphery region, the semiconductor device comprises a first annular wall 111 reaching to the diffusion layer 104 through the first interlayer insulating film 110, a first annular pad 112 provided on the first interlayer insulating film 110 and connected to the first annular wall 111, a second annular wall 115 reaching to the first annular pad 112 through the second interlayer insulating film 114, a second annular pad 116 provided on the second interlayer insulating film 114 and connected to the second annular wall 115, a third annular wall 119 reaching to the second annular pad 116 through the third interlayer insulating film 118, a third annular pad 120 provided on the third interlayer insulating film 118 and connected to the third annular wall 119, a fourth annular wall 122 reaching to the third annular pad 120 through the fourth interlayer insulating film 121, and a fourth annular pad 123 provided on the fourth interlayer insulating film 121 and connected to the fourth annular wall 122. Each of the annular walls 111, 115, 119, and 122 and each of the annular pads 112, 116, 120 and 123 described above configure a seal ring for stopping the intrusion of moisture and humidity into the internal element region.
FIG. 10 is a cross sectional view for showing a comparison between the structures of the chip area outer periphery region and the internal element region in the conventional semiconductor device. As shown in the same figure, the first annular wall 111 in the chip area outer periphery region is formed by filling a contact hole with metal or polycrystalline silicon at the same time as a contact plug 151 in the internal element region. The first annular pad 112 is formed by patterning a metal film at the same time as local wiring 152 in the internal element region. The second annular wall 115 in the chip area outer periphery region is formed by filling a via hole with metal at the same time as a first via plug 155 in the internal element region. The second annular pad 116 is formed by patterning a metal film at the same time as a first layer wiring 156 in the internal element region. The third annular wall 119 in the chip area outer periphery region is formed by filling a via hole with metal at the same time as a second via plug 159 in the internal element region. The third annular pad 120 is formed by patterning a metal film at the same time as a second layer wiring 160 in the internal element region. The fourth annular wall 122 in the chip area outer periphery region is formed by filling a via hole with metal at the same time as a third via plug 162 in the internal element region. The fourth annular pad 123 and third layer wiring 163 in the internal element region are formed by patterning a metal film at the same time.
Herein, a coating film used as the interlayer insulating film is generally an organic film. Even in the case of using a film containing an inorganic substance as main constituent, such as a silica film, an organic component is often additively used therein so as to suppress the occurrence of cracks during sintering. Further, even in the use of a silica film, which could be turned into an almost perfectly inorganic silicon oxide film by sintering at about 800° C., when the silica film is formed on wiring, the organic component added as a solvent is left in the film without being perfectly eliminated, because heat treatment is limited to about 400° C. In this way, an insulating film containing an organic component is inherently high in absorptivity for moisture or water permeability. Therefore, if after formed into a film, the coating film is exposed, moisture comes to be easily incorporated into the interior of the semiconductor device, thus causing a deterioration in reliability of the semiconductor device.
For this reason, in the conventional semiconductor device shown in FIGS. 8 to 10, the outer periphery of the internal element region is enclosed with a seal ring composed of the annular pad and annular wall, thereby providing a configuration in which moisture is prevented from entering into interlayer insulating films, even after semiconductor chips have been separately cut and divided in scribe regions.
However, when attempting to form the conventional semiconductor device described above by using a dual damascene process, the following problems may be conceived.
That is, in a dual damascene process, after the opening of a ring-shaved groove for use in an annular wall (for example, the third annular wall 119) on the upper layer side and a hole for use in a plug (for example, the second via plug 159) on the upper layer side, during a dry etching process for forming an annular groove for use in an annular pad (for example, the third annular pad 120) on the upper layer side and a groove for use in wiring (for example, the second layer wiring 160) on the upper layer side, there exist the annular grooves, openings, having a large area. For this reason, there has been a fear that serious plasma damage is caused to wiring (for example, the local wiring 152 and the first layer wiring 156) on the lower layer side and the silicon substrate. Also, at this time, Cu and the like are released as gas from an portion exposed at the bottom of the annular groove in an annular pad (for example, the second annular pad 116) of the lower layer, and thus variations in the dry etching rate have been resulted sometimes. As a result, variations have been caused in the depth of grooves for use in wiring (for example, the second layer wiring 160) in the internal element region, thus resulting in a fear that variations may occur in wiring resistance.